82P33831_17 Datasheet, PDF (8/12 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet

82P33831 Datasheet
Table 1: Pin Description (Continued)
Pin No.
B12
A10
B10
E9
G9
H9
J9
B11
C11
D9
E5
D10
C5
F1
K3
G1
L3
Name
XTAL1_OUT
XTAL2_IN
XTAL2_OUT
DPLL3_LOCK
DPLL2_LOCK
DPLL1_LOCK
INT_REQ
MPU_MODE1/
I2CM_SCL
MPU_MODE0/
I2CM_SDA
I2C_AD2
I2C_AD1
I2C_SCL
I2C_SDA
TMS
TRSTB
TCK
TDI
I/O
O
I
O
O
O
O
O
Tri-state
I/O
pull-up
I
pull-down
I
pull-down
I
I/O
I
pull-up
I
pull-up
I
pull-down
I
pull-up
Type
Description
Analog
Analog
Analog
Crystal oscillator 1 output.
Leave open if XTAL1 is not used.
Crystal oscillator 2 input.
Determines first of two frequency families (chosen from Sonet/SDH, Ethernet or Ethernet*66/
64) available for APLL3. Connect to ground if XTAL2 is not used
Crystal oscillator 2 output.
Leave open if XTAL2 is not used.
Lock Signal
CMOS
DPLL3_LOCK
This pin goes high when DPLL3 is locked
CMOS
CMOS
DPLL2_LOCK
This pin goes high when DPLL2 is locked
DPLL1_LOCK
This pin goes high when DPLL1 is locked
Microprocessor Interface
CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request.
MPU_MODE[1:0]: Microprocessor Interface Mode Selection
During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-
lows:
00: I2C mode
CMOS/ ^{01 ~ 10: Reserved}
Open Drain ^{11: I2C master (EEPROM) mode}
I2CM_SCL: Serial Clock Line
In I2C master mode, the serial clock is output on this pin.
I2CM_SDA: Serial Data Input for I2C Master Mode
In I2C master mode, this pin is used as the for the serial data.
CMOS
I2C_AD2: Device Address Bit 2
I2C_AD[2:1] pins are the address bus of the microprocessor interface.
CMOS
I2C_AD1: Device Address Bit 1
I2C_AD[2:1] pins are the address bus of the microprocessor interface.
CMOS
I2C_SCL: Serial Clock Line
The serial clock is input on this pin.
Open Drain
I2C_SDA: Serial Data Input/Output
This pin is used as the input/output for the serial data.
JTAG (per IEEE 1149.1)
CMOS
CMOS
CMOS
CMOS
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
TRSTB: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
TDI: JTAG Test Data Input
The test data are input on this pin. They are clocked into the device on the rising edge of
TCK.
©2017 Integrated Device Technology, Inc.
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Revision 7, December 8, 2016