82P33831_17 Datasheet, PDF (4/12 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet

FUNCTIONAL BLOCK DIAGRAM
LOS0 / XO_FREQ0
LOS1 / XO_FREQ1
LOS2 / XO_FREQ2
LOS3
IN1(CC)
IN2(CC)
IN3(P/N)
IN4(P/N)
IN5(P/N)
IN6(P/N)
IN7(P/N)
IN8(P/N)
IN9
IN10
IN11
IN12
IN13
IN14
System Clock
SYS PLL
Composite
Clocks
Reference
monitors
Reference
selection
Frac-N input
dividers
ToD/ Time
Accumulator
DPLL1 /
DCO1
DPLL2 /
DCO2
ToD/ Time
Accumulator
APLL1
APLL2
DPLL3
ex_sync module
I2C Master
I2C Slave
Control and
Status
Registers
JTAG
APLL3
(VCXO)
Crystal
Figure 1. Functional Block Diagram
82P33831 Datasheet
OutDiv
OutDiv
OutDiv
OutDiv
OUT1
OUT2
OUT3p/n
OUT4p/n
OutDiv
OutDiv
OutDiv
Composite
Clock
OutDiv
OutDiv
OutDiv
OutDiv
OUT5p/n
OUT6p/n
OUT7
OUT8
OUT9
OUT10
OUT11p/n
OUT12p/n
FRSYNC_8K_1PPS
MFRSYNC_2K_1PPS
©2017 Integrated Device Technology, Inc.
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Revision 7, December 8, 2016