82P33831_17 Datasheet, PDF (7/12 Pages) Integrated Device Technology – Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet

82P33831 Datasheet
Table 1: Pin Description (Continued)
Pin No.
J10
H10
G10
F10
E11
E10
E12
C12
L8
K5
M5
M6
M1
M2
A1
A2
A3
A4
C4
M9
M10
D12
D11
A8
B8
A6
B6
C9, A9, D8
A12
Name
IN9
IN10
IN11
IN12
IN13
IN14
FRSYNC
_8K_1PPS
MFRSYNC
_2K_1PPS
OUT1
OUT2
OUT3_POS
OUT3_NEG
OUT4_POS
OUT4_NEG
OUT5_POS
OUT5_NEG
OUT6_POS
OUT6_NEG
OUT7
OUT8_POS
OUT8_NEG
OUT9
OUT10
OUT11_POS
OUT11_NEG
OUT12_POS
OUT12_NEG
CAP1, CAP2,
CAP3
XTAL1_IN
I/O
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
I
pull-down
O
O
O
Type
Description
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
IN9: Input Clock 9
A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN10: Input Clock 10
A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN11: Input Clock 11
A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN12: Input Clock 12
A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN13: Input Clock 13
A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
IN14: Input Clock 14
A reference clock is input on this pin. This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
Output Frame Synchronization Signal
CMOS
CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS sync signal is output on this pin.
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
A 2 kHz signal or a 1PPS sync signal is output on this pin.
Output Clock
CMOS ^{OUT1 ~ OUT2: Output Clock 1 ~ 2}
O
PECL/LVDS
OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3
This output is set to LVDS by default. The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
This output is set to LVDS by default. The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
This output is set to LVDS by default. The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
This output is set to LVDS by default. The LVDS output has internal 100 ohm termination.
O
CMOS OUT7: Output Clock 7
OUT8_POS / OUT8_NEG: Positive / Negative Output Composite Clock
O
AMI A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this
pair of pins.
O
CMOS OUT9: Output Clock 9
O
CMOS OUT10: Output Clock 10
O
PECL/LVDS ^{OUT11_POS / OUT11_NEG: Positive / Negative Output Clock 11}
O
PECL/LVDS ^{OUT12_POS / OUT12_NEG: Positive / Negative Output Clock 12}
Miscellaneous
CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3. These capacitors
are be part of the power filtering.
Crystal oscillator 1 input.
I
Analog Determines first of two frequency families (Sonet/SDH, Ethernet or Ethernet*66/64) available
for APLL3. Connect to ground if XTAL1 is not used.
©2017 Integrated Device Technology, Inc.
11
Revision 7, December 8, 2016