7134SA55J Datasheet, PDF (8/12 Pages) Integrated Device Technology – HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM

IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage⁽⁵⁾
7134X20
Com'l Only
Symbol
Parameter
WRITE CYCLE
tWC
Write Cycle Time
tEW
Chip Enable to End-of-Write
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time
tWP
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Valid to End-of-Write
tHZ
Output High-Z Time ^(1,2)
tDH
Data Hold Time⁽³⁾
tWZ
Write Enable to Output in High-Z^(1,2)
tOW
Output Active from End-of-Write ^(1,2,3)
tWDD
Write Pulse to Data Delay⁽⁴⁾
tDDD
Write Data Valid to Read Data Delay⁽⁴⁾
Min.
Max.
20
____
15
____
15
____
0
____
15
____
0
____
15
____
____
15
0
____
____
15
3
____
____
40
____
30
7134X25
Com'l & Ind
Min.
Max.
25
____
20
____
20
____
0
____
20
____
0
____
15
____
____
15
0
____
____
15
3
____
____
50
____
30
7134X35
Com'l
& Military
Min.
Max. Unit
35
____
ns
30
____
ns
30
____
ns
0
____
ns
25
____
ns
0
____
ns
20
____
ns
____
20
ns
3
____
ns
____
20
ns
3
____
ns
____
60
ns
____
35
ns
2720 tbl 10a
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
45
____
55
____
70
____
ns
tEW
Chip Enable to End-of-Write
40
____
50
____
60
____
ns
tAW
Address Valid to End-of-Write
40
____
50
____
60
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWP
Write Pulse Width
40
____
50
____
60
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
25
____
30
____
ns
tHZ
Output High-Z Time^(1,2)
tDH
Data Hold Time⁽³⁾
____
20
____
25
____
30
ns
3
____
3
____
3
____
ns
tWZ
Write Enable to Output in High-Z^(1,2)
____
20
____
25
____
30
ns
tOW
Output Active from End-of-Write ^(1,2,3)
tWDD
Write Pulse to Data Delay⁽⁴⁾
3
____
3
____
3
____
ns
____
70
____
80
____
90
ns
tDDD
Write Data Valid to Read Data Delay⁽⁴⁾
____
45
____
55
____
70
ns
NOTES:
2720 tbl 10b
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. 'X' in part number indicates power rating (SA or LA).
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