5962-3829407MXA Datasheet, PDF (8/10 Pages) Integrated Device Technology – CMOS Static RAM 64K (8K x 8-Bit)

IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)^(1,5)
tWC
ADDRESS
CS2
CS1
WE
DATAOUT
DATAIN
tAW
tAS
tWR1(2)
(3)
tWHZ(6)
tWP ⁽⁵⁾
tOW(6)
tDW
tDH1,2
DATA VALID
2967 drw 08
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)⁽¹⁾
tWC
ADDRESS
tAS
tWR2(2)
CS2
CS1
tCW
(4)
tWR1(2)
tAW
WE
tDW
tDH1,2
DATAIN
DATA VALID
2967 drw 09
NOTES:
1. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2.
2. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to
turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum
write pulse width is as short as the specified tWP.
6. Transition is measured ±200mV from steady state.
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