5962-3829407MXA Datasheet, PDF (5/10 Pages) Integrated Device Technology – CMOS Static RAM 64K (8K x 8-Bit)

IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
7164S20
7164L20
7164S25
7164L25
Symbol
Parameter
Min. Max. Min. Max. ^Unit
Read Cycle
tRC
Read Cycle Time
20
____
25
____
ns
tAA
Address Access Time
____
19
____
25 ns
tACS1⁽¹⁾ Chip Select-1 Access Time
____
20
____
25 ns
tACS2⁽¹⁾ Chip Select-2 Access Time
____
25
____
30 ns
tCLZ1,2⁽²⁾ Chip Select-1, 2 to Output in Low-Z
5
____
5
____
ns
tOE
Output Enable to Output Valid
____
8
____
12 ns
tOLZ⁽²⁾
Output Enable to Output in Low-Z
0
____
0
____
ns
tCHZ1,2⁽²⁾ Chip Select-1,2 to Output in High-Z
____
9
____
13 ns
tOHZ⁽²⁾
Output Disable to Output in High-Z
____
8
____
10 ns
tOH
Output Hold from Address Change
5
____
5
____
ns
tPU⁽²⁾
Chip Select to Power Up Time
0
____
0
____
ns
tPD⁽²⁾
Chip Deselect to Power Down Time
____
20
____
25 ns
Write Cycle
tWC
Write Cycle Time
20
____
25
____
ns
tCW1,2 Chip Select to End-of-Write
15
____
18
____
ns
tAW
Address Valid to End-of-Write
15
____
18
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
tWP
Write Pulse Width
tWR1
Write Recovery Time (CS1, WE)
15
____
0
____
21
____
ns
0
____
ns
tWR2
Write Recovery Time (CS2)
5
____
5
____
ns
tWHZ⁽²⁾
Write Enable to Output in High-Z
____
8
____
10 ns
tDW
Data to Write Time Overlap
tDH1
Data Hold from Write Time (CS1, WE)
10
____
13
____
ns
0
____
0
____
ns
tDH2
Data Hold from Write Time (CS2)
5
____
5
____
ns
tOW⁽²⁾
Output Active from End-of-Write
4
____
4
____
ns
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
2967 tbl 12
6.542