8T49N286 Datasheet, PDF (77/78 Pages) Integrated Circuit Systems – Bypass clock paths for system tests

8T49N286 DATA SHEET
Revision History Sheet
Rev Table
2
Table 12
3
T7F
T12
4
5
Page
P4
60
22
51
62
65
12
Description of Change
Block Diagram - corrected divide symbol.
AC Characteristics Table - updated LVDS Rise/Fall Time maximum spec. from 500 to
400ps.
Miscellaneous content enhancement in:
Output Phase Control on Switchover section; Table 7A, Table 7C, Table 7E and Table 7G,
Table 7S and “Pin Assignment” format.
Digital PLL0 Feedback Control Register Bit Field Table - deleted ACQBW0[3:0]’s “0000 =
512mHz”
AC Characteristics Table - added missing minimum Output Frequency spec for Q2, Q3
(LVPECL, LVDS) and LVCMOS.
“Termination for 3.3V LVPECL Outputs” - updated Figure 13A.
“Crystal Recommendation” - included additional crystal recommendation.
Deleted IDT prefix/suffix throughout the datasheet.
Device Start-up & Reset Behavior - added second paragraph.
Date
12/8/14
3/17/15
5/6/15
7/8/15
REVISION 5 07/08/15
77
FEMTOCLOCK^® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR