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8T49N286 Datasheet, PDF (69/78 Pages) Integrated Circuit Systems – Bypass clock paths for system tests
Table 17G. 3.3V LVCMOS Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Base_Current (mA)
37.4
61.6
40.6
Table 17H. 2.5V LVCMOS Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Base_Current (mA)
30.8
54.8
33.7
8T49N286 DATA SHEET
Table 17I. 1.8V LVCMOS Output Calculation Table
Output
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Base_Current (mA)
27.4
51.4
30.3
Applying the values to the following equation will yield output current by frequency:
Qx Current (mA) = FQ_Factor * Frequency (MHz) + Base_Current
where:
Qx Current is the specific output current according to output type and frequency
FQ_Factor is used for calculating current increase due to output frequency
Base_Current is the base current for each output path independent of output frequency
The second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following
equation:
TJ = TA + (JA * Pdtotal)
where:
TJ is the junction temperature (°C)
TA is the ambient temperature (°C)
JA is the thermal resistance value from Table 16, dependent on ambient airflow (°C/W)
Pdtotal is the total power dissipation of the 8T49N286 under usage conditions, including power dissipated due to loading (W).
Note that the power dissipation per output pair due to loading is assumed to be 27.95mW for LVPECL outputs and 44.5mW for HCSL outputs.
When selecting LVCMOS outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace
length. For these examples, power dissipation through loading will be calculated using CPD (found in Table 2) and output frequency:
PdOUT = CPD * FOUT * VCCO2
where:
PdOUT is the power dissipation of the output (W)
CPD is the power dissipation capacitance (pF)
FOUT is the output frequency of the selected output (MHz)
VCCO is the voltage supplied to the appropriate output (V)
REVISION 5 07/08/15
69
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