8T49N286 Datasheet, PDF (36/78 Pages) Integrated Circuit Systems – Bypass clock paths for system tests

8T49N286 DATA SHEET
Table 7M. Output Clock Source Control Register Bit Field Locations and Descriptions
Output Clock Source Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
D0
00A8
Rsvd
PLL1_SYN PLL0_SYN CLK_SEL3 CLK_SEL2 CLK_SEL1 CLK_SEL0
00A9
Rsvd
CLK_SEL5[2:0]
Rsvd
CLK_SEL4[2:0]
00AA
Rsvd
CLK_SEL7[2:0]
Rsvd
CLK_SEL6[2:0]
00AB
11
11
Rsvd
Rsvd
Bit Field Name
PLL1_SYN
PLL0_SYN
CLK_SEL0
CLK_SEL1
CLK_SEL2
CLK_SEL3
CLK_SEL4[2:0]
CLK_SEL5[2:0]
Output Clock Source Control Register Block Field Descriptions
Field Type Default Value Description
Output Synchronization Control for Outputs Derived from PLL1.
Setting this bit from 01 will cause the output divider(s) for the affected outputs to
R/W
0b
be held in reset.
Setting this bit from 10 will release all the output divider(s) for the affected
outputs to run from the same point in time with the coarse output phase
adjustment reset to 0.
Output Synchronization Control for Outputs Derived from PLL0.
Setting this bit from 01 will cause the output divider(s) for the affected outputs to
R/W
0b
be held in reset.
Setting this bit from 10 will release all the output divider(s) for the affected
outputs to run from the same point in time with the coarse output phase
adjustment reset to 0.
Clock Source Selection for output Q0, nQ0:
R/W
0b
0 = PLL0
1 = PLL1
Clock Source Selection for output Q1, nQ1:
R/W
1b
0 = PLL0
1 = PLL1
Clock Source Selection for output Q2, nQ2:
R/W
0b
0 = PLL0
1 = PLL1
Clock Source Selection for output Q3, nQ3:
R/W
1b
0 = PLL0
1 = PLL1
Clock Source Selection for output Q4, nQ4: Do not select Input Reference 0, 1 or 2
if that input is faster than 250MHz:
000 = PLL0
001 = PLL1
R/W
000b
010 = Output Q2, nQ2
011 = Output Q3, nQ3
100 = Input Reference 0 (CLK0)
101 = Input Reference 1 (CLK1)
110 = Input Reference 2 (CLK2)
111 = Crystal Input
Clock Source Selection for output Q5, nQ5: Do not select Input Reference 0, 1 or 2
if that input is faster than 250MHz:
000 = PLL0
001 = PLL1
R/W
010b
010 = Output Q2, nQ2
011 = Output Q3, nQ3
100 = Input Reference 0 (CLK0)
101 = Input Reference 1 (CLK1)
110 = Input Reference 2 (CLK2)
111 = Crystal Input
FEMTOCLOCK^® NG OCTAL UNIVERSAL FREQUENCY TRANSLATOR
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REVISION 5 07/08/15