92HD66C Datasheet, PDF (71/291 Pages) Integrated Device Technology – SIX CHANNEL HD AUDIO CODECS

92HD66C
SIX CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
Field Name
Mono0
PhAdj
Rate
Bits
R/W
Default
Reset
4
RW
0h
POR
DMic0 mono select: 0 = stereo operation, 1 = mono operation (left channel du-
plicated to the right channel).
3:2
RW
0h
POR
Selects what phase of the DMic clock the data should be latched:
0h = left data rising edge/right data falling edge
1h = left data center of high/right data center of low
2h = left data falling edge/right data rising edge
3h = left data center of low/right data center of high
1:0
RW
2h
POR
Selects the DMic clock rate:
0h = 4.704MHz
1h = 3.528MHz
2h = 2.352MHz
3h = 1.176MHz.
6.7.21. AFG (NID = 01h): DACMode
Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8)
Set
Get
F8000h
Byte 1 (Bits 7:0)
780h
Field Name
Rsvd
SDMSettleDisable
SDMCoeffSel
SDMLFHalf
Bits
R/W
Default
Reset
31:8
R
000000h
N/A (Hard-coded)
Reserved.
7
RW
0h
POR
SDM wait-to-settle disable:
1 = at mute, the SDM switches to the mute pattern immediately
0 = at mute, the SDM switches to the mute pattern after settling (can take up to
~45ms)
6
RW
0h
POR
DAC SDM coefficient select (stages 1, 2, 3):
1 = 1/16, 1/2, 1/4
0 = 1/16, 1/4, 1/2
5
RW
0h
POR
DAC SDM local feedback coefficient select: 1 = 1/4096, 0 = 1/2048.
IDT CONFIDENTIAL
71
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92HD66C