ICSSSTVA16859C Datasheet, PDF (7/10 Pages) Integrated Device Technology – DDR 13-Bit to 26-Bit Registered Buffer

ICSSSTVA16859C
Timing Requirements¹
(over recommended operating free-air temperature range, unless otherwise noted)
SYMBOL
PARAMETERS
V_DDQ = 2.5V ± 0.2V
MIN
MAX
f_clock Clock frequency
270
t_SL Output slew rate
1
4
t_S
Setup time, fast slew rate ^{2 & 4}
Setup time, slow slew rate ^{3 & 4}
Data before CLK↑ , CLK#↓
0.4
0.6
T_h
Hold time, fast slew rate ^{2 & 4}
Hold time, slow slew rate ^{3 & 4}
Data after CLK↑ , CLK#↓
0.4
0.5
Notes: 1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of ≥ 1V/ns.
3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rate of ≥ 1V/ns.
UNITS
MHz
V/ns
ns
ns
ns
ns
Switching Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
SYMBOL
From
(Input)
To
(Output)
V_DD = 2.5V ±0.2V
UNITS
MIN
TYP MAX
f_max
t_PD
CLK, CLK# (TSSOP)
CLK, CLK# (VFQFN[MLF2])
Q
Q
210
MHz
1.6
2.1
2.6
ns
1.6
2.1
2.6
ns
t_phl RESET#
Q
3.5
ns
Switching Characteristics - DDRI-400 (PC3200)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
SYMBOL
From
(Input)
To
(Output)
V_DD = 2.6V ±0.1V
UNITS
MIN
TYP MAX
f_max
t_PD
t_PDSS
t_PD
t_phl
(VFQFN[MLF2])
CLK, CLK# (TSSOP)
RESET#
210
MHz
Q
1.1
1.65
ns
Q
1.9
ns
Q
1.1
1.6 1.85
ns
Q
3.5
ns
1114A—05/26/05
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