ICS9FG107 Datasheet, PDF (7/18 Pages) Integrated Circuit Systems – Programmable FTG for Differential CPU, PCI Express & SATA Clocks

ICS9FG107
Programmable FTG for Differential P4^TM CPU, PCI-Express & SATA Clocks
I²C Table: Frequency Select Readback Register
Byte 3
Pin #
Name
Control Function Type
0
1
Bit 7
27
SEL14M_25M#¹
State of pin 27
R
(FS3)
See Frequency
Bit 6
5
FS2¹
State of pin 6
R Selection Table, Page 1
Bit 5
44
FS1¹
State of pin 44
R
Bit 4
7
FS0¹
State of pin 7
R
Bit 3
26
SPREAD¹
State of pin 26
R
Off
On
Bit 2
RESERVED
R
RESERVED
Bit 1
RESERVED
R
RESERVED
Bit 0
45
DWNSPRD¹
State of pin 45
R
Down
Center
Notes:
1. These read-only bits always reflect the latched state of the corresponding pins at power up.
PWD
Pin 27
Pin 5
Pin 44
Pin 7
Pin 26
X
X
Pin 45
I²C Table: Vendor & Revision ID Register
Byte 4
Pin #
Name
Control Function Type
0
Bit 7
-
RID3
R
-
Bit 6
-
Bit 5
-
RID2
RID1
REVISION ID
R
-
R
-
Bit 4
-
RID0
R
-
Bit 3
-
VID3
R
-
Bit 2
-
Bit 1
-
VID2
VID1
VENDOR ID
R
-
R
-
Bit 0
-
VID0
R
-
1
PWD
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
1
I²C Table: DEVICE ID
Byte 5
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
Control Function
Device ID = 07 Hex
Bit 7 is MSB
Type
R
R
R
R
R
R
R
R
0
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PWD
0
0
0
0
0
1
1
1
IDT^TM/ICS^TM Programmable FTG for Differential P4^TM CPU, PCI-Express & SATA Clocks
7
ICS9FG107 REV F 08/21/07