ICS9FG107 Datasheet, PDF (3/18 Pages) Integrated Circuit Systems – Programmable FTG for Differential CPU, PCI Express & SATA Clocks

ICS9FG107
Programmable FTG for Differential P4^TM CPU, PCI-Express & SATA Clocks
Pin Description
PIN #
1
2
3
4
5
6
PIN NAME
XIN/CLKIN
X2
VDD
GND
FS2/REFOUT*
GND
7
FS0/PCICLK_F*
8
PCICLK0
9
PCICLK1
10
VDD
11
OE_6**
12
DIF_6
13
DIF_6#
14
VDD
15
GND
16
OE_5**
17
DIF_5
18
DIF_5#
19
VDD
20
DIF_4
21
DIF_4#
22
OE_4*
23
SDATA
24
SCLK
PIN TYPE
IN
OUT
PWR
PWR
I/O
PWR
I/O
OUT
OUT
PWR
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
I/O
IN
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Frequency select latch input pin / Reference clock output
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Power supply, nominal 3.3V
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
Active high input for enabling output 5.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 4.
0 = tri-state outputs, 1= enable outputs
Data pin for SMBus circuitry, 3.3V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
IDT^TM/ICS^TM Programmable FTG for Differential P4^TM CPU, PCI-Express & SATA Clocks
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ICS9FG107 REV F 08/21/07