ICS98ULPA877A Datasheet, PDF (7/14 Pages) Integrated Device Technology – 1.8V Low-Power Wide-Range Frequency Clock Driver

ICS98UL PA8 77A
Advance Information
Switching Characteristics¹
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
Output enable time
t_en
OE to any output
Output disable time
t_dis
OE to any output
Period jitter
t_{jit (per)}
Half-period jitter
Input slew rate
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Static Phase Offset
t _{jit (per) +} t _{(Ø)dyn +} t _skew(o)
t_{(Ø)dyn +} t_skew(o)
Output to Output Skew
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
t_jit(hper)
SLr1(i)
SLr1(o)
t_jit(cc+)
t_jit(cc-)
t_(Ø)dyn
t_SPO2
∑_(su)
∑_{t (h)}
t_skew
Input Clock
Output Enable (OE), (OS)
(MHz)
MIN
160 to 410
160 to 270 -40
271 to 410 -30
160 to 270 -60
271 to 410 -50
1
0.5
160 to 410 1.5
0
0
160 to 270 -50
271 to 410 -20
271 to 410 -50
160 to 270
271 to 410
30.00
0.00
2.0
TYP
4.73
5.82
2.5
2.5
0
MAX
8
8
40
30
60
50
4
3
40
-40
50
20
50
80
60
40
30
33
-0.50
UNITS
ns
ns
ps
ps
ps
ps
v/ns
v/ns
v/ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
kHz
%
MHz
Notes:
1. Switching characteristics guaranteed for application frequency range.
2. Static phase offset shifted by design.
1177C—05/23/07
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