ICS98ULPA877A Datasheet, PDF (6/14 Pages) Integrated Device Technology – 1.8V Low-Power Wide-Range Frequency Clock Driver

ICS98UL PA8 77A
Advance Information
Timing Requirements
Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C;
Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Max clock frequency
freq_op
1.8V+0.1V @ 25°C
95
Application Frequency
Range
freq_App
1.8V+0.1V @ 25°C
160
Input clock duty cycle
d_tin
40
CLK stabilization
T_STAB
MAX UNITS
410 MHz
410 MHz
60
%
15
µs
NOTE: The PLL must be able to handle spread spectrum induced skew.
NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters. (Used for low speed system debug.)
NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters.
NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal, within the value specificied by the Static Phase Offset (t∅), after power-up. During
normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock
of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode
and later return to active operation. CK and CK# may be left floating after they have been driven low for one
complete clock cycle.
1177C—05/23/07
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