ICS93732 Datasheet, PDF (7/8 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS9373 2
N
c
INDEX
AREA
E1 E
12
D
A2
e
b
A
A1
-C-
SEATING
PLANE
.10 (.004) C
209 mil SSOP
L
α
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN
MAX
--
2.00
0.05
--
1.65
1.85
0.22
0.38
0.09
0.25
SEE VARIATIONS
7.40
8.20
5.00
5.60
0.65 BASIC
0.55
0.95
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
--
.079
.002
--
.065
.073
.009
.015
.0035
.010
SEE VARIATIONS
.291
.323
.197
.220
0.0256 BASIC
.022
.037
SEE VARIATIONS
0°
8°
VARIATIONS
N
28
D mm.
MIN
MAX
9.90
10.50
Reference Doc.: JEDEC Publication 95, MO-150
10-0033
D (inch)
MIN
MAX
.390
.413
Ordering Information
ICS93732yFLFT
Example:
ICS XXXX y F LF T
0578J—06/20/08
Designation for tape and reel packaging
RoHS Compliant
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
7