ICS93732 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS9373 2
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PIN NAME
DDRC0
DDRT0
VDD
DDRT1
DDRC1
GND
SCLK
CLK_INT
N/C
VDDA
GND
VDD
DDRT2
DDRC2
GND
DDRC3
DDRT3
N/C
FB_OUT
20
FB_INT
21
N/C
22
SDATA
23
VDD
24
DDRT4
25
DDRC4
26
DDRT5
27
DDRC5
28
GND
PIN TYPE DESCRIPTION
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
N/C
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
N/C
OUT
IN
N/C
I/O
PWR
OUT
OUT
OUT
OUT
PWR
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
Ground pin.
Clock pin of I2C circuitry 5V tolerant
"True" reference clock input.
No Connection.
2.5V power for the PLL core.
Ground pin.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
Ground pin.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
No Connection.
Feedback output, dedicated for external feedback.
True single-ended feedback input, provides feedback
signal to internal PLL for synchronization with CLK_INT
to eliminate phase error.
No Connection.
Data pin for I2C circuitry 5V tolerant
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
Ground pin.
0578J—06/20/08
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