ICS93732 Datasheet, PDF (4/8 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS9373 2
Timing Requirements
T_A = 0 - 70°C; Supply Voltage AV_DD, V_DD = 2.50V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating Clock Frequency freqop Input Voltage level: 0-2.50V
22
Input Clock Duty Cycle¹
d_tin
40
Clock Stabilization¹
t_STAB from VDD = 2.5V to 1% target frequency
340 MHz
50 60
%
100 µs
1. Guaranteed by design, not 100% tested in production.
Switching Characteristics
T_A = 0 - 70°C; Supply Voltage AV_DD, V_DD = 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Cycle to cycle Jitter^1,2
Phase Error¹
Output to output Skew¹
t_c-c
t_pe
T_skew
66 MHz
100 / 125/ 133/167MHz
200/267MHz
-150
Duty Cycle (Sign Ended)^1,3
DC
66 MHz to 100MHz
49.5
101MHz to 267 MHz
49
Rise Time, Fall Time⁴
t_R , t_f
Load=120Ω/14pF
TYP
100
48
47
20
50
49.4
579
MAX
120
65
75
150
100
50.5
51
950
UNITS
ps
ps
ps
%
%
ps
Notes:
1. Refers to transition on noninverting output.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=t_wH/t_c, where
the cycle (t_c) decreases as the frequency goes up.
0578J—06/20/08
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