ICS932S805C Datasheet, PDF (7/19 Pages) Integrated Device Technology – K8 Clock Chip for Serverworks HT2100 Servers

ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
SMBus Table: Frequency Select and Spread Control Register
Byte 0 Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-
Bit 6
-
FS Source
Latched Input or SMBus Frequency _{RW Latched Inputs SMBus}
0
Select
Spread
Spread Enable for CPU, SRC and PCI Outputs.
Spectrum
Setting SPREAD_EN pin to '1', forces RW
OFF
ON
0
Enable
Spread ON and overides this bit.
Bit 5
-
Reserved
Reserved
RW Reserved Reserved
0
Bit 4
-
Reserved
Reserved
RW Reserved Reserved
0
Bit 3
-
FS3
Bit 2
-
FS2
Bit 1
-
FS1
Bit 0
-
FS0
Freq Select Bit 3
Freq Select Bit 2
Freq Select Bit 1
Freq Select Bit 0
RW
Latched
RW See CPU Frequency Select Latched
RW
Table
Latched
RW
Latched
SMBus Table: Output Control Register
Byte 1 Pin #
Name
Bit 7
6
REF2
Bit 6
5
REF1
Bit 5
4
REF0
Bit 4
17
PCICLK1
Bit 3
16
PCICLK0
Bit 2
11
48MHz_2
Bit 1
10
48MHz_1
Bit 0
9
48MHz_0
Control Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
0
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
RW Disable (Low)
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
1
1
1
1
1
1
1
1
SMBus Table: Output Control Register
Byte 2 Pin #
Name
Bit 7
-
Reserved
Bit 6 59/58
CPUCLK8(6)
Bit 5 57/56
CPUCLK8(5)
Bit 4 53/52
CPUCLK8(4)
Bit 3 51/50
CPUCLK8(3)
Bit 2 47/46
CPUCLK8(2)
Bit 1 45/44
CPUCLK8(1)
Bit 0 43/42
CPUCLK8(0)
Control Function
Reserved
Output Enable
When Disabled
CPUCLKT = 0
CPUCLKC = 1
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Reserved
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Reserved
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
IDT^® K8 Clock Chip for Serverworks HT2100 Servers
7
1131D – 05/04/10