ICS932S805C Datasheet, PDF (10/19 Pages) Integrated Device Technology – K8 Clock Chip for Serverworks HT2100 Servers

ICS932S805C
K8 Clock Chip for Serverworks HT2100 Servers
Bytes 11:14 Are Reserved
SMBus Table: CPU/SRC Frequency Control Register
Byte 15 Pin #
Name
Control Function
Bit 7
-
N Div8
N Divider Prog bit 8
Bit 6
-
N Div9
N Divider Prog bit 9
Bit 5
-
M Div5
Bit 4
-
M Div4
Bit 3
-
M Div3
M Divider Programming
Bit 2
-
M Div2
bit (5:0)
Bit 1
-
M Div1
Bit 0
-
M Div0
Type
0
1
RW
The decimal representation
RW _{of M and N Divier in Byte 15}
RW _{and 16 will configure the}
RW CPU VCO frequency.
RW ^{Default at power up = latch-}
RW ^{in or Byte 0 Rom table. VCO}
RW
Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: CPU/SRC Frequency Control Register
Byte 16 Pin #
Name
Control Function
Type
0
1
Bit 7
-
Bit 6
-
Bit 5
-
N Div7
N Div6
N Div5
RW
The decimal representation
RW _{of M and N Divier in Byte 15}
RW _{and 16 will configure the}
Bit 4
-
N Div4
N Divider Programming Byte12 bit(7:0) RW CPU VCO frequency.
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
N Div3
N Div2
N Div1
N Div0
and Byte11 bit(7:6)
RW ^{Default at power up = latch-}
RW ^{in or Byte 0 Rom table. VCO}
RW
Frequency = 14.318 x
[NDiv(9:0)+8] / [MDiv(5:0)+2]
RW
PWD
X
X
X
X
X
X
X
X
SMBus Table: CPU/SRC Spread Spectrum Control Register
Byte 17 Pin #
Name
Control Function
Type
0
1
Bit 7
-
SSP7
RW
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
RW _{These Spread Spectrum bits}
RW
in Byte 17 and 18 will
Spread Spectrum Programming bit(7:0) ^RW
program the spread
RW _{pecentage of CPU and SRC}
RW
outputs.
RW
Bit 0
-
SSP0
RW
PWD
X
X
X
X
X
X
X
X
IDT^® K8 Clock Chip for Serverworks HT2100 Servers
10
1131D – 05/04/10