ICS87421I Datasheet, PDF (7/14 Pages) Integrated Device Technology – ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

ICS87421I
÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF in
single ended levels. The reference voltage V_REF = V /2 is
DD
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT^™ / ICS^™ LVDS CLOCK GENERATOR
7
ICS87421AMI REV. A OCTOBER 3, 2007