ICS87421I Datasheet, PDF (1/14 Pages) Integrated Device Technology – ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

÷1/÷2 DIFFERENTIAL-TO-LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87421I is a high performance ÷1/÷2
ICS
Differential-to-LVDS Clock Generator and a mem-
HiPerClockS™ _{ber of the HiPerClockS™ family of High Perfor-}
mance Clock Solutions from IDT. The CLK, nCLK
pair can accept most standard differential input
levels. The ICS87421I is characterized to operate from a 3.3V
power supply. Guaranteed part-to-part skew characteristics
make the ICS87421I ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
ICS87421I
FEATURES
• One differential LVDS output
• One differential CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum clock input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVDS levels with resistor bias on nCLK input
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.7ns (maximum)
• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK
nCLK
MR
÷1 0
Q
nQ
R ^{÷2 1}
F_SEL
PIN ASSIGNMENT
CLK 1
nCLK 2
MR 3
F_SEL 4
8 VDD
7Q
6 nQ
5 GND
ICS87421I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
IDT^™ / ICS^™ LVDS CLOCK GENERATOR
1
ICS87421AMI REV. A OCTOBER 3, 2007