ICS8308I Datasheet, PDF (7/16 Pages) Integrated Circuit Systems – Low Skew, 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer

ICS8308I
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
TABLE 5C. AC CHARACTERISTICS, V_DD = V_DDO = 2.5V±5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
350
Propagation
t_PD
Delay;
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
IJ 350MHz
IJ 350MHz
1.5
1.7
4.2
4.4
tsk(o) Output Skew; NOTE 3, 7
Measured on
rising edge @V_DDO/2
160
tsk(pp) Part-to-Part Skew; NOTE 4, 7
Measured on
rising edge @V_DDO/2
2
t_R / t_F
Output Rise/Fall Time
0.6V to 1.8V
0.2
1.0
odc
Output Duty Cycle
IJ 150MHz, Ref = CLK, nCLK
40
60
t_PZL, t_PZH Output Enable Time; NOTE 5
5
t_PLZ, t_PHZ
t_S
Output Disable Time; NOTE 5
Clock Enable
Setup Time;
NOTE 6
CLK_EN to
CLK, nCLK
CLK_EN to
LVCMOS_CLK
5
1
0
t_H
Clock Enable
Hold Time;
NOTE 6
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
0
1
NOTE 1: Measured from the differential input crossing point to V_DDO/2 of the output.
NOTE 2: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ns
ns
%
ns
ns
ns
ns
ns
ns
IDT^™ / ICS^™ LVCMOS FANOUT BUFFER
7
ICS8308AGI REV. B OCTOBER 16, 2007