ICS8308I Datasheet, PDF (5/16 Pages) Integrated Circuit Systems – Low Skew, 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer

ICS8308I
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
TABLE 4F. DC CHARACTERISTICS, V_DD, V_DDO = 2.5V±5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions Minimum Typical
V_IH
Input High Voltage
LVCMOS
2
LVCMOS_CLK
-0.3
V_IL
Input Low Voltage
CLK_EN, OE
I_IN
Input Current
V_IN = V_DD or
V_IN = GND
V_OH
Output High Voltage; NOTE 1
I_OH = -15mA
1.8
V_OL
Output Low Voltage; NOTE 1
I_OL = 15mA
V_PP
V_CMR
Peak-to-Peak Input Voltage CLK, nCLK
Input Common Mode Voltage;
NOTE 2, 3
CLK, nCLK
0.15
GND + 0.5
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to V_DDO/2.
See Parameter Measurement section, "3.3V Output Load AC Test Circuit".
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V_DD + 0.3V.
NOTE 3: Common mode voltage is defined as V .
IH
Maximum
V_DD + 0.3
1.3
0.7
300
0.6
1.3
V_DD - 0.85
Units
V
V
V
µA
V
V
V
V
TABLE
5A.
AC
CHARACTERISTICS,
V
DD
=
V
DDO
=
3.3V±5%,
TA
=
-40°
TO
85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
350
Propagation
t_PD
Delay;
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
IJ 350MHz
IJ 350MHz
2
2
4
4
tsk(o) Output Skew; NOTE 3, 7
Measured on
rising edge @V_DDO/2
100
tsk(pp) Part-to-Part Skew; NOTE 4, 7
Measured on
rising edge @V /2
1
DDO
t_R / t_F
Output Rise/Fall Time
0.8V to 2V
0.2
1
odc
Output Duty Cycle
IJ 150MHz, Ref = CLK, nCLK
45
55
t_PZL, t_PZH Output Enable Time; NOTE 5
5
t_PLZ, t_PHZ
t
S
Output Disable Time; NOTE 5
Clock Enable
Setup Time;
NOTE 6
CLK_EN to
CLK, nCLK
CLK_EN to
LVCMOS_CLK
5
1
0
Clock Enable
CLK, nCLK to
CLK_EN
0
t_H
Hold Time;
NOTE 6
LVCMOS_CLK
to CLK_EN
1
NOTE 1: Measured from the differential input crossing point to V_DDO/2 of the output.
NOTE 2: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ns
ns
%
ns
ns
ns
ns
ns
ns
IDT^™ / ICS^™ LVCMOS FANOUT BUFFER
5
ICS8308AGI REV. B OCTOBER 16, 2007