ICS8308I Datasheet, PDF (2/16 Pages) Integrated Circuit Systems – Low Skew, 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer

ICS8308I
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 11, 13, 15,
17, 19, 21, 23
Q0, Q1, Q7, Q6,
Q5, Q4,Q3, Q2
Output
Clock outputs. LVCMOS / LVTTL interface levels.
2, 10, 14, 18, 22
GND
Power
Power supply ground.
Clock select input. Selects LVCMOS clock input when HIGH.
3
CLK_SEL
Input Pullup Selects CLK, nCLK inputs when LOW. See Table 3A.
LVCMOS / LVTTL interface levels.
4
LVCMOS_CLK Input Pullup Clock input. LVCMOS / LVTTL interface levels.
5
CLK
Input Pullup Non-inverting differential clock input.
6
nCLK
Input Pulldown Inverting differential clock input.
7
CLK_EN
Input Pullup Clock enable. LVCMOS / LVTTL interface levels.
8
OE
Input
Pullup
Output enable. LVCMOS / LVTTL interface levels.
See Table 3B.
9
V_DD
Power
Core supply pin.
12, 16, 20, 24
V_DDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
C_PD
R_PULLUP
R_PULLDOWN
R_OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
5
Typical
4
12
51
51
7
Maximum
12
Units
pF
pF
kΩ
kΩ
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
CLK_SEL
0
1
Clock Input
CLK, nCLK is selected
LVCMOS_CLK is selected
TABLE 3B. OE SELECT FUNCTION TABLE
Control Input
OE
0
1
Output Operation
Outputs Q0:Q7 are in Hi-Z (disabled)
Outputs Q0:Q7 are active (enabled)
TABLE 3C. CLOCK INPUT FUNCTION TABLE
Inputs
CLK_SEL LVCMOS_CLK
CLK
nCLK
Outputs
Q0:Q7
Input to Output Mode
Polarity
0
—
0
1
LOW Differential to Single Ended Non Inverting
0
—
1
0
HIGH Differential to Single Ended Non Inverting
0
—
0
Biased; NOTE 1 LOW Single Ended to Single Ended Non Inverting
0
—
1
Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inverting
0
—
Biased; NOTE 1
0
HIGH Single Ended to Single Ended Inverting
0
—
Biased; NOTE 1
1
LOW Single Ended to Single Ended Inverting
1
0
—
—
LOW Single Ended to Single Ended Non Inverting
1
1
—
—
HIGH Single Ended to Single Ended Non Inverting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
IDT^™ / ICS^™ LVCMOS FANOUT BUFFER
2
ICS8308AGI REV. B OCTOBER 16, 2007