ICS83023I Datasheet, PDF (7/13 Pages) Integrated Device Technology – DUAL, 1-TO-1 DIFFERENTIAL-TOLVCMOS TRANSLATOR/BUFFER

ICS83023I _ICS83023I
Integrated
Circuit
D , 1- -1 _{DUAL, 1-TO-1 DIFSFyEsRtEemNTsI,AILn-cT.O-LVCMOS TRANSLATOR/BUFFER}
D - -LVCMOS T /B IFFERENTIAL TO
UAL TO _TSD
RANSLATOR UFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and V_DD = 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
VDD
Single Ended Clock Input
V_REF
C1
0.1u
R1
1K
CLK
nCLK
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
83023AMI
www.icst.com/products/hiperclocks.html
7
IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
7
REV. B JANUARY 18, 2006
ICS83023I