ICS83023I Datasheet, PDF (4/13 Pages) Integrated Device Technology – DUAL, 1-TO-1 DIFFERENTIAL-TOLVCMOS TRANSLATOR/BUFFER

ICS83023I _ICS83023I
Integrated
Circuit
D , 1- -1 _{DUAL, 1-TO-1 DIFSFyEsRtEemNTsI,AILn-cT.O-LVCMOS TRANSLATOR/BUFFER}
D - -LVCMOS T /B IFFERENTIAL TO
UAL TO _TSD
RANSLATOR UFFER
TABLE 4. AC CHARACTERISTICS, V_DD = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
t_PD
tsk(o)
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
350
1.8
2.1
2.4
60
tsk(pp) Part-to-Part Skew; NOTE 3, 4
500
tjit
Buffer Additive Phase Jitter, RMS;
100MHz, Integration Range
refer to Additive Phase Jitter Section
(637kHz-10MHz)
0.14
t_R
Output Rise Time
t_F
Output Fall Time
odc
Output Duty Cycle
0.8V to 2V
0.8V to 2V
f ≤ 166MHz
f > 166MHz
100
250
400
100
250
400
45
50
55
43
50
57
All parameters measured at f_MAX unless noted otherwise. See Parameter Measurement Information.
NOTE 1: Measured from the differential input crossing point to V_DD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DD/2. Input clocks are phase aligned.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V_DD/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
ps
%
%
83023AMI
www.icst.com/products/hiperclocks.html
4
IDT™ / ICS™ DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
4
REV. B JANUARY 18, 2006
ICS83023I