83918 Datasheet, PDF (7/19 Pages) Integrated Device Technology – Maximum output frequency

83918 DATA SHEET
Table 5D. AC Characteristics, V_DD = V_DDO = 2.5V±5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
f_OUT
tp_LH
Output Frequency
Propagation Delay, Low to High;
NOTE 1
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz
tjit
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz
tsk(o)
Output Skew; NOTE 3, 6
tsk(pp) Part-to-Part Skew; NOTE 4, 6
t_R / t_F
odc
Output Rise/Fall Time; NOTE 5
Output Duty Cycle
20% to 80%
ƒ_OUT  150MHz
Minimum
2
Typical
Maximum
200
3
Units
MHz
ns
0.478
ps
0.157
ps
75
ps
1
ns
300
700
ps
45
55
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f_OUT unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
Table 5E. AC Characteristics, V_DD = 2.5V±5%,V_DDO = 1.8V±0.2V, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
f_OUT
Output Frequency
tp_LH
Propagation Delay, Low to High;
NOTE 1
1.75
tjit(Ø)
RMS Phase Jitter, (Random);
NOTE 2
25MHz,
Integration Range: 1kHz to 1MHz
tjit
Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
155.52MHz,
Integration Range: 12kHz to 20MHz
tsk(o)
Output Skew; NOTE 3, 6
tsk(pp) Part-to-Part Skew; NOTE 4, 6
t_R / t_F
Output Rise/Fall Time; NOTE 5
20% to 80%
200
odc
Output Duty Cycle
ƒ_OUT  150MHz
45
Typical
0.591
0.175
Maximum
200
3.85
75
1.15
800
55
Units
MHz
ns
ps
ps
ps
ns
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f_OUT unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Refer to the Phase Noise Plot following this section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 4: Defined as the skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
LOW SKEW, 1:18 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
7
Rev B 3/25/15