ZSSC1750 Datasheet, PDF (68/116 Pages) Integrated Device Technology – Data Acquisition System Basis Chip

ZSSC1750 / ZSSC1751 Datasheet
The chop clock is generated from the SDM clock by further dividing it by 2, 4, 8, or 16 depending on the setting
of the sdmChopClkDiv field in register adcGomd:
f = f ∗ 2 _CHOP
SDM
−(sdmChopClkDiv +1)
(8)
Both the SMD and chop clocks are generated from the same 125kHz clock that is used for the digital logic.
Shifting of the clocks used to generate the SDM and chop clock is not possible and not needed as the analog
clocks are generated on the falling clock edge where the digital logic is already stable and will not influence the
analog section.
Figure 3.17 LP/ULP ADC Clocking Scheme; sdmClkDivLp = 5; sdmChopClkDiv = 0
CLK_LPOSC
SDM clock
CHOP clock
3.8.1.3 Register “sdmClkCfgLp” – Configuration Register for the SDM Clocks in the LP/ULP State
Table 3.23 Register sdmClkCfgLp
Name
sdmClkDivLp[7:0]
sdmClkDivLp[9:8]
Unused
Address
B0_HEX
B1_HEX
Bits
[7:0]
[1:0]
Default
18_HEX
00_BIN
Access
RW
RW
[7:2] 00 0000_BIN RO
Description
Clock divider value for the SDM clock in the LP
and ULP States related to the 125KHz base clock.
With sdmClkDivLP = 0, the divider value is 2.
Unused; always write as 0.
3.8.1.4 Register “sdmClkCfgFp” – Configuration Register for the SDM Clocks in the FP State
Table 3.24 Register sdmClkCfgFp
Name
sdmClkDivFp[7:0]
sdmClkDivFp[9:8]
Unused
sdmPos2
sdmPos
Address
B2_HEX
B3_HEX
Bits
[7:0]
[1:0]
[2]
[5:3]
[7:6]
Default
08_HEX
00_BIN
0_BIN
010_BIN
10_BIN
Access
RW
RW
RO
RW
RW
Description
Clock divider value for the SDM clock in the FP
State related to the 4MHz base clock f_HP.
If 0, then the SDM clock is 2MHz.
Unused; always write as 0
Position of the chop clock (CLK_CHOPBASE) relative
to the base clock CLK_MUXCLK (possible values = 0
to 4)
Position of the SDM clock (CLK_SDMBASE) relative to
the base clock CLK_MUXCLK
© 2016 Integrated Device Technology, Inc.
68
April 20, 2016