ZSSC1750 Datasheet, PDF (27/116 Pages) Integrated Device Technology – Data Acquisition System Basis Chip

ZSSC1750 / ZSSC1751 Datasheet
SSW[4]:
Current ADC active
SSW[3]:
LIN short protection active (applicable for ZSSC1750 only)
SSW[2]:
LIN TXD timeout protection active (applicable for ZSSC1750 only)
SSW[1]:
Readable sleep timer value valid
SSW[0]:
OTP download procedure active
Note: After the external microcontroller has been reset, the user’s software can read the low-voltage flag and the
reset status by a single-byte transfer (important: send only the address byte) to shorten the initialization phase
(e.g., when a reset was caused by a wake-up event) without needing to read or write further bytes including the
length byte.
After the address byte and length byte are sent by the master, either the master (write transfer) or the slave
(read transfer) is transmitting data. The slave ignores all incoming bits while it is sending the requested number
of data bytes (read), and the data bytes returned during a write transfer have no meaning. Figure 3.1 shows a
read and a write burst access to the SBC.
Figure 3.1 Read and Write Burst Access to the SBC
Read Access
SCLK
CSN
MOSI
A[7:0]
R
L[6:0]
MISO
Write Access
SCLK
SSW[11:0]
D0[7:0]
CSN
MOSI
MISO
A[7:0]
W
L[6:0]
SSW[11:0]
D0[7:0]
A:
Start address of SPI access
R:
Read access (MSB of second byte is low)
W: Write access (MSB of second byte is high)
L:
Number of data bytes (0 = 128 bytes)
SSW: Slave status word
SCLK: SPI clock
DL-1[7:0]
DL-1[7:0]
© 2016 Integrated Device Technology, Inc.
27
April 20, 2016