ZSSC1750 Datasheet, PDF (49/116 Pages) Integrated Device Technology – Data Acquisition System Basis Chip

ZSSC1750 / ZSSC1751 Datasheet
3.7 SBC Power Management Unit (SBC_PMU Block)
The power management unit (PMU) controls placing the SBC into the selected power down state, controlling the
power down signals for the different analog blocks, and controlling the clocks for the digital logic. It also controls
the other digital modules during the power-down state.
The system provides four different power states:
FP (Full-Power State)
In this state, all blocks are powered except the ADCs if the user’s software has
not enabled them. All internal clocks are active (divClk and muxClk are 4MHz)
and the external microcontroller is also powered and clocked through pins
VDDP, VDDC, and MCU_CLK. When powered and enabled by software, the
ADC clocks are generated from the clock from the high-precision oscillator.
LP (Low-Power State)
In this state, the high-precision oscillator and the LIN transmitter (ZSSC1750
only) are powered down. The clock for the external microcontroller (MCU_CLK)
is stopped, but the microcontroller remains powered through VDDP and/or
VDDC. Depending on the selected measurement scenario, the ADCs are also
powered down during times of inactivity. Otherwise the ADC clocks are
generated from the low-power oscillator.
ULP (Ultra-Low-Power State) In this state, the high-precision oscillator and the LIN transmitter (ZSSC1750
only) are powered down. The optional external microcontroller clock MCU_CLK
is stopped and the supply voltages for the external microcontroller (VDDP,
VDDC) are powered down. Depending on the selected measurement scenario,
the ADCs are also powered down during times of inactivity. Otherwise, the
ADC clocks are generated from the clock from the low-power oscillator.
OFF (Off State)
In this state, all analog blocks except the digital power supply for the SBC and
the RX part of the LIN PHY (ZSSC1750 only) are powered down. The external
microcontroller clock MCU_CLK is stopped, and the supply voltages for the
external microcontroller (VDDP, VDDC) are powered down.
For the ZSSC1750/51 to enter any of the power-down states (LP, ULP, or OFF), the user’s software must first
set the pdState field of register pwrCfgLp to select the state (see Table 3.19) and enable the interrupts
needed as the wakeup source before writing A9_HEX to register gotoPd (see Table 3.20). Immediately after A9_HEX
is written to the gotoPd register, the CSN line must be driven high. Although for all other register accesses, the
CSN line can be kept low and the next SPI transfer can follow immediately, it is mandatory to drive CSN high for
the power-down command. Otherwise, the PMU remains in the FP State.
Important: If no interrupt is enabled, the system can only be awakened by power-on-reset!
Note: The CSN line must be driven high to go to power-down after writing the value A9_HEX to register gotoPd.
© 2016 Integrated Device Technology, Inc.
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April 20, 2016