IDT82P2284_08 Datasheet, PDF (60/363 Pages) –

IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
3.10.2 E1 MODE
The Remote alarm, Remote Signaling Multi-Frame alarm, RED
alarm, AIS alarm, AIS in TS16 and LOS in TS16 are detected in this
block.
The Remote Alarm Indication bit is the A bit (refer to Table 18). It is
detected on the base of Basic frame synchronization. The criteria of
Remote alarm detection are defined by the RAIC bit. If the RAIC bit is
‘0’, the Remote alarm will be declared when 4 consecutive A bits are
received as ‘1’, and the Remote alarm will be cleared when a single A bit
is received as ‘0’. If the RAIC bit is ‘1’, the Remote alarm will be declared
when a single A bit is received as ‘1’, and the Remote alarm will be
cleared when a single A bit is received as ‘0’. The Remote alarm status
is reflected by the RAIV bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’)
on the RAIV bit will set the RAII bit to ‘1’ and the RAII bit will be cleared
by writing a ‘1’. A ‘1’ in the RAII bit means there is an interrupt. The inter-
rupt will be reported by the INT pin if the RAIE bit is ‘1’.
The Remote Signaling Multi-Frame Alarm Indication bit is the Y bit
(refer to Figure 13). It is detected on the base of CAS Signaling Multi-
Frame synchronization. The Remote Signaling Multi-Frame alarm will be
declared when 3 consecutive Y bits are received as ‘1’, and the Remote
Signaling Multi-Frame alarm will be cleared when a single Y bit is
received as ‘0’. The Remote Signaling Multi-Frame alarm status is
reflected by the RMAIV bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’)
on the RMAIV bit will set the RMAII bit to ‘1’ and the RMAII bit will be
cleared by writing a ‘1’. A ‘1’ in the RMAII bit means there is an interrupt.
The interrupt will be reported by the INT pin if the RMAIE bit is ‘1’.
The criteria of RED alarm detection meet I.431. The RED alarm will
be declared when out of Basic frame synchronization persists for 100
ms, and the RED alarm will be cleared when in Basic frame synchroni-
zation persists for 100 ms. The RED alarm status is reflected by the
RED bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the RED bit will
set the REDI bit to ‘1’ and the REDI bit will be cleared by writing a ‘1’. A
‘1’ in the REDI bit means there is an interrupt. The interrupt will be
reported by the INT pin if the REDE bit is ‘1’.
The AIS alarm is detected whether it is in synchronization or not. The
criteria of AIS alarm are defined by the AISC bit. When the AISC bit is
‘0’, the criteria meet I.431. The AIS alarm will be declared when less
than 3 zeros are detected in a 512-bit fixed window and it is out of Basic
frame synchronization, and the AIS alarm will be cleared when more
than 2 zeros are detected in a 512-bit fixed window. When the AISC bit
is ‘1’, the criteria meet G.775. The AIS alarm will be declared when less
than 3 zeros are detected in each of 2 consecutive 512-bit fixed
windows, and the AIS alarm will be cleared when more than 2 zeros are
detected in each of 2 consecutive 512-bit fixed windows. The AIS alarm
status is reflected by the AIS bit. Any transition (from ‘0’ to ‘1’ or from ‘1’
to ‘0’) on the AIS bit will set the AISI bit to ‘1’ and the AISI bit will be
cleared by writing a ‘1’. A ‘1’ in the AISI bit means there is an interrupt.
The interrupt will be reported by the INT pin if the AISE bit is ‘1’.
The AIS in TS16 is detected on the base of Basic frame synchroniza-
tion. The AIS in TS16 will be declared when TS16 contains less than 4
zeros in each of two 16-consecutive-Basic-frame periods. The AIS in
TS16 will be cleared when TS16 contains more than 3 zeros in a 16-
consecutive-Basic-frame period. The AIS in TS16 status is reflected by
the TS16AISV bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the
TS16AISV bit will set the TS16AISI bit to ‘1’ and the TS16AISI bit will be
cleared by writing a ‘1’. A ‘1’ in the TS16AISI bit means there is an inter-
rupt. The interrupt will be reported by the INT pin if the TS16AISE bit is
‘1’.
The LOS in TS16 is detected on the base of Basic frame synchroni-
zation. The LOS in TS16 will be declared when 16 consecutive TS16 are
all received as ‘0’. The LOS in TS16 will be cleared when 16 consecutive
TS16 are not all received as ‘0’. The LOS in TS16 status is reflected by
the TS16LOSV bit. Any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the
TS16LOSV bit will set the TS16LOSI bit to ‘1’ and the TS16LOSI bit will
be cleared by writing a ‘1’. A ‘1’ in the TS16LOSI bit means there is an
interrupt. The interrupt will be reported by the INT pin if the TS16LOSE
bit is ‘1’.
Table 28: Related Bit / Register In Chapter 3.10.2
Bit
RAIC
AISC
RAIV
RMAIV
RED
AIS
TS16AISV
TS16LOSV
RAII
RMAII
REDI
AISI
TS16AISI
TS16LOSI
RAIE
RMAIE
REDE
AISE
TS16AISE
TS16LOSE
Register
E1 Address (Hex)
Alarm Criteria Control 0BC, 1BC, 2BC, 3BC
Alarm Status
0B9, 1B9, 2B9, 3B9
Alarm Indication
0BB, 1BB, 2BB, 3BB
Alarm Control
0BA, 1BA, 2BA, 3BA
Functional Description
60
February 25, 2008