IDT82P2284_08 Datasheet, PDF (269/363 Pages) –

IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
E1 RBIF Bit Offset (04AH, 14AH, 24AH, 34AH)
Bit No.
7
Bit Name
Type
Default
6
5
Reserved
4
3
2
1
0
EDGE
BOFF2
BOFF1
BOFF0
R/W
R/W
R/W
R/W
0
0
0
0
EDGE:
This bit is valid when the CMS bit (b1, E1-046H,...) is ‘1’.
= 0: The first active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSDA(MRSDB) and RSIGn/MRSIGA(MRSIGB) pins.
= 1: The second active edge of RSCKn/MRSCK is selected to update the data on the RSDn/MRSDA(MRSDB) and RSIGn/MRSIGA(MRSIGB)
pins.
BOFF[2:0]:
Except that in the Receive Master mode, when the OHD bit (b3, E1-048H,...), the SMFS bit (b2, E1-048H,...) and the CMFS bit (b1, E1-048H,...)
are set to TS1 and TS16 overhead indication, the bit offset is supported in all the other conditions.
These bits give a binary number to define the bit offset. The bit offset is between the framing pulse on the RSFSn/MRSFS pin and the start of the
corresponding frame output on the RSDn/MRSDA(MRSDB) pin. The signaling bits on the RSIGn/MRSIGA(MRSIGB) pin are always per-channel
aligned with the data on the RSDn/MRSDA(MRSDB) pin.
E1 RTSFS Change Indication (04BH, 14BH, 24BH, 34BH)
Bit No.
7
6
5
4
3
2
Bit Name
Type
Reserved
Default
RCOFAI:
This bit is valid in Receive Clock Slave mode and Receive Multiplexed mode.
= 0: The interval of the pulses on the RSFSn/MRSFS pin is an integer multiple of 125 µs.
= 1: The interval of the pulses on the RSFSn/MRSFS pin is not an integer multiple of 125 µs.
This bit will be cleared if a ’1’ is written to it.
TCOFAI:
This bit is valid in Transmit Clock Slave mode and Transmit Multiplexed mode.
= 0: The pulse on the TSFSn/MTSFS pin is an integer multiple of 125 µs.
= 1: The pulse on the TSFSn/MTSFS pin is not an integer multiple of 125 µs.
This bit will be cleared if a ’1’ is written to it.
1
RCOFAI
R
0
0
TCOFAI
R
0
Programming Information
269
February 25, 2008