IDT82P2284_08 Datasheet, PDF (116/363 Pages) –

IDT82P2284
QUAD T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
4 OPERATION
4.1 POWER-ON SEQUENCE
To power on the device, the following sequence should be followed:
• Apply ground;
• Apply 3.3 V;
• Apply 1.8 V.
4.2 RESET
When the device is powered-up, all the registers contain random
values.
The hardware reset pin RESET must be asserted low during the
power-up and the low signal should last at least 10 ms to initialize the
device. After the RESET pin is asserted high, all the registers are in their
default values and can be accessed after 2 ms (refer to Figure 37).
During normal operation, the device can be reset by hardware or
software anytime. When it is hardware reset, the RESET pin should be
asserted low for at least 100 ns. Then all the registers are in their default
values and can be accessed after 2 ms (refer to Figure 38). When it is
software reset, a write signal to the Software Reset register will reset all
the registers except the T1/J1 Or E1 Mode register to their default
values. Then the registers are accessible after 2 ms. However, the T1/J1
Or E1 Mode register can not be reset by the software reset. It can only
be reset by the hardware reset.
It should be mentioned that when the setting in the T1/J1 Or E1
Mode register is changed, a software reset must be applied.
Vdd
10ms
RESET
Microprocessor
Interface
2ms
access
Figure 37. Hardware Reset When Powered-Up
100 ns
RESET
Microprocessor
Interface
2ms
access
Figure 38. Hardware Reset In Normal Operation
4.3 RECEIVE / TRANSMIT PATH POWER DOWN
The receive path of any of the four links can be power down by
setting the R_OFF bit. During the receive path power down, the output
of the corresponding path is low.
The transmit path of any of the four links can be set to power down
by the T_OFF bit. During the transmit path power down, the output of the
corresponding path is High-Z.
4.4 MICROPROCESSOR INTERFACE
The microprocessor interface provides access to read and write the
registers in the device. The interface consists of Serial Peripheral Inter-
face (SPI) and parallel microprocessor interface.
Operation
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February 25, 2008