IDT82P2281_09 Datasheet, PDF (60/371 Pages) Integrated Device Technology – Single T1/E1/J1 Long Haul / Short Haul Transceiver

IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
Channel 24
Channel 1
Channel 2
RSD/MRSD 1 2 3 4 5 6 7 8 F 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Channel 24
Channel 1
1 2 3 4 5 6 7 8F1 2 3 4 5 6 7 8
RSIG/MRSIG
ABCD
ABCD
ABCD
ABCD
ABCD
F-bit
F-bit
Figure 16. Signaling Output In T1/J1 Mode
3.15.2 E1 MODE
In Signaling Multi-Frame, the signaling bits are located in TS16
(refer to Figure 13), which are Channel Associated Signalings (CAS).
The signaling codewords (ABCD) are clocked out on the RSIG/MRSIG
pins. They are in the lower nibble of the timeslot with its corresponding
data serializing on the RSD/MRSD pins (as shown in Figure 17).
When the EXTRACT bit is set to ‘1’, the signaling bits in its corre-
sponding timeslot are extracted to the A,B,C,D bits in the Extracted Sig-
naling Data/Extract Enable register. The data in the A,B,C,D bits in the
register are the data to be output on the RSIG/MRSIG pins. The bits cor-
responding to TS0 and TS16 output on the RSIG/MRSIG pins are Don’t-
Care.
Signaling de-bounce will be executed when the DEB bit is set to ‘1’.
Thus, the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register are updated only if 2 consecutive received ABCD codewords of
the same timeslot are identical.
Signaling freezing is performed automatically when it is out of Basic
frame synchronization, out of Signaling multi-frame synchronization or
slips occurs in the Elastic Store Buffer. It is also performed when the
FREEZE bit is set to ‘1’. The signaling freezing freezes the signaling
data in the A,B,C,D bits in the Extracted Signaling Data/Extract Enable
register as the previous valid value.
Each time the extracted signaling bits in the A,B,C,D bits in the
Extracted Signaling Data/Extract Enable register are changed, it is cap-
tured by the corresponding COSI[X] bit (1 ≤ X ≤ 30). When the SIGE bit
is set to ‘1’, any one of the COSI[X] bits being ‘1’ will generate an inter-
rupt and will be reported by the INT pin.
The EXTRACT bit and the A,B,C,D bits are in the indirect registers
of the Receive CAS/RBS Buffer. They are accessed by specifying the
address in the ADDRESS[6:0] bits. Whether the data is read from or
written into the specified indirect register is determined by the RWN bit
and the data is in the D[7:0] bits. The access status is indicated in the
BUSY bit. Refer to Chapter 4.5 Indirect Register Access Scheme for
details about the indirect registers write/read access.
TS31
TS0
TS1
TS15
TS16
TS17
TS31
TS0
RSD/MRSD 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78
RSIG/MRSIG
ABCD
ABCD
ABCD
ABCD
Figure 17. Signaling Output In E1 Mode
ABCD
Functional Description
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August 20, 2009