IDT82P2281_09 Datasheet, PDF (104/371 Pages) Integrated Device Technology – Single T1/E1/J1 Long Haul / Short Haul Transceiver

IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
4 OPERATION
4.1 POWER-ON SEQUENCE
To power on the device, the following sequence should be followed:
1. Apply ground;
2. Apply 3.3 V;
3. Apply 1.8 V.
4.2 RESET
When the device is powered-up, all the registers contain random
values.
The hardware reset pin RESET must be asserted low during the
power-up and the low signal should last at least 10 ms to initialize the
device. After the RESET pin is asserted high, all the registers are in their
default values and can be accessed after 2 ms (refer to Figure 36).
During normal operation, the device can be reset by hardware or
software anytime. When it is hardware reset, the RESET pin should be
asserted low for at least 100 ns. Then all the registers are in their default
values and can be accessed after 2 ms (refer to Figure 37). When it is
software reset, a write signal to the Software Reset register will reset all
the registers except the T1/J1 Or E1 Mode register to their default val-
ues. Then the registers are accessible after 2 ms. However, the T1/J1
Or E1 Mode register can not be reset by the software reset. It can only
be reset by the hardware reset.
Hardware or software reset can only be applied when the clock on
the OSCI pin is available.
It should be mentioned that when the setting in the T1/J1 Or E1
Mode register is changed, a software reset must be applied.
RESET
Microprocessor
Interface
100 ns
2ms
access
Figure 37. Hardware Reset In Normal Operation
4.3 RECEIVE / TRANSMIT PATH POWER DOWN
The receive path can be power down by setting the R_OFF bit.
During the receive path power down, the output is low.
The transmit path can be set to power down by the T_OFF bit. Dur-
ing the transmit path power down, the output is High-Z.
Vdd
10ms
RESET
Microprocessor
Interface
2ms
access
Figure 36. Hardware Reset When Powered-Up
Operation
104
August 20, 2009