ICS950910 Datasheet, PDF (6/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4

Integrated
Circuit
Systems, Inc.
ICS950910
Byte 0: Functionality and frequency select register (Default=0)
Bit
Description
PWD
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
Bit2
Bit7
FS3
Bit6
FS2
Bit5
FS1
Bit4
FS0
CPUCLK AGPCLK PCICLK
MHz MHz MHz
Spread %
0 0 0 0 0 102.00 68.00 34.00 +/- 0.30% Center Spread
0 0 0 0 1 105.00 70.00 35.00 +/- 0.30% Center Spread
0 0 0 1 0 108.00 72.00 36.00 +/- 0.30% Center Spread
0 0 0 1 1 111.00 74.00 27.00 +/- 0.30% Center Spread
0 0 1 0 0 114.00 76.00 38.00 +/- 0.30% Center Spread
0 0 1 0 1 117.00 78.00 39.00 +/- 0.30% Center Spread
0 0 1 1 0 120.00 80.00 40.00 +/- 0.30% Center Spread
0 0 1 1 1 123.00 82.00 41.00 +/- 0.30% Center Spread
0 1 0 0 0 126.00 72.00 36.00 +/- 0.30% Center Spread
0 1 0 0 1 130.00 74.30 37.10 +/- 0.30% Center Spread
0 1 0 1 0 133.90 66.95 33.48 +/- 0.30% Center Spread
0 1 0 1 1 140.00 70.00 35.00 +/- 0.30% Center Spread
0 1 1 0 0 144.00 72.00 36.00 +/- 0.30% Center Spread
0 1 1 0 1 148.00 74.00 37.00 +/- 0.30% Center Spread
0 1 1 1 0 152.00 76.00 38.00 +/- 0.30% Center Spread
0 1 1 1 1 156.00 78.00 39.00 +/- 0.30% Center Spread
1 0 0 0 0 105.00 70.00 35.00
0.3 % Center Spread
1 0 0 0 1 140.00 70.00 35.00
0.3 % Center Spread
1 0 0 1 0 210.00 70.00 35.00
0.3 % Center Spread
1 0 0 1 1 174.99 70.00 35.00
0.3 % Center Spread
1 0 1 0 0 80.00 53.34 26.66
0.3 % Center Spread
1 0 1 0 1 106.66 53.34 26.66
0.3 % Center Spread
1 0 1 1 0 160.00 53.34 26.66
0.3 % Center Spread
1 0 1 1 1 133.33 53.34 26.66
0.3 % Center Spread
1 1 1 0 0 100.00 66.67 33.33
0.3 % Center Spread
1 1 1 0 1 133.33 66.67 33.33
0.3 % Center Spread
1 1 1 1 0 200.00 66.67 33.33
0.3 % Center Spread
1 1 1 1 1 166.66 66.67 33.33
0.3 % Center Spread
1 1 0 0 0 100.00 66.67 33.33 0 - 0.6% Down Spread
1 1 0 0 1 133.33 66.67 33.33 0 - 0.6% Down Spread
1 1 0 1 0 200.00 66.67 33.33 0 - 0.6% Down Spread
1 1 0 1 1 166.66 66.67 33.33 0 - 0.6% Down Spread
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2,7:4
0 - Normal
1 - Spread spectrum enable
0 - Running
1 - Tristate all outputs
Note 1
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Mode Pin - Power Management Input Control
MODE, Pin 6
(Latched Input)
0
1
Pin 26
PD#
(Input)
RESET#
(Output)
Pin 18
CPU_STOP#
(Input)
PCICLK5
(Output)
Pin 8
PCI_STOP#
(Input)
AGP2
(Output)
0735B—09/21/07
6