English
Language : 

ICS950910 Datasheet, PDF (13/21 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for P4
Integrated
Circuit
Systems, Inc.
ICS950910
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
VIH
2
TYP MAX
VDD + 0.3
Input Low Voltage
VIL
VSS - 0.3
0.8
Input High Current
Input Low Current
IIH
VIN = VDD; Inputs with no pull-down
resistors
IIH
VIN = VDD; Inputs with pull-down
resistors
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5.75
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
5.75
200
IDD3.3OP CL = Full load; Select @ 100 MHz 228
156
360
Operating Supply Current
IDD3.3OP
CL =Full load; Select @ 133 MHz
220
159
360
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance1
Clk Stabilization1,2
IDD3.3PD
Fi
Lpin
CIN
COUT
CINX
TSTAB
IREF=2.32 mA
VDD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From PowerUp or deassertion of
PowerDown to 1st clock.
12
45
14.318
7
5
6
27
45
2.1
tPZH,tPZL Output enable delay (all outputs)
1
12
Delay1
tPHZ,tPLZ Output disable delay (all outputs)
1
12
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for buffered and un-buffered timing requirements.
UNITS
V
V
mA
µA
mA
µA
mA
mA
mA
MHz
nH
pF
pF
pF
ms
ns
ns
0735B—09/21/07
13