ICS93716 Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Clock Driver

ICS9371 6
Timing Requirements
T_A = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R_L = 120Ω, C_L=15pF (unless otherwise
PARAMETER
SYMBOL
CONDITIONS
MIN MAX UNITS
Max clock frequency³
freq_op
33
233 MHz
Application Frequency
Range³
freq_App
60
170 MHz
Input clock duty cycle
d_tin
40
60
%
CLK stabilization
T_STAB
100
µs
Switching Characteristics
T_A = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R_L = 120 , C_L=15pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN TYP MAX UNITS
Low-to high level
propagation delay time
t_PLH1
CLK_IN to any output
5.5
ns
High-to low level propagation
delay time
t_PHL1
CLK_IN to any output
5.5
ns
Duty Cycle
DC
49
51
%
Input clock slew rate
Cycle to Cycle Jitter¹
Cycle to Cycle Jitter¹
Phase error
t_sl(I)
t_cyc-t_cyc
t_cyc-t_cyc
t_(phase
4
error)
100MHz < f < 170MHz
f=66MHz
1
-150
4
v/ns
50
65
ps
72
75
ps
0
150 ps
Output to Output Skew
t_skew
75
100 ps
Rise Time, Fall Time
Notes:
t_r, t_f
See figure 8
550
950 ps
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t_wH/t_c, were
the cycle (t_c) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0420H—09/10/08
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