ICS8432-101_07 Datasheet, PDF (6/20 Pages) Integrated Device Technology – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
CLK
I_IH
Input High Current
nCLK
V_CC = V_IN = 3.465V
V_CC = V_IN = 3.465V
I_IL
CLK
Input Low Current
nCLK
V_CC = 3.465V, V_IN = 0V
V_CC = 3.465V, V_IN = 0V
-5
-150
V_PP
Peak-to-Peak Input Voltage
0.15
V_CMR
Common Mode Input Voltage
V_EE + 0.5
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is V_CC + 0.3V.
NOTE 2: Common mode voltage is defined as V .
IH
Maximum
150
5
1.3
V_CC - 0.85
Units
µA
µA
µA
µA
V
V
TABLE 4D. LVPECL DC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
V_OH
Output High Voltage; NOTE 1
V
Output Low Voltage; NOTE 1
OL
V_SWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to V_CCO - 2V.
V_CCO - 1.4
V - 2.0
CCO
0.6
Typical
Maximum
V_CCO - 0.9
V - 1.7
CCO
1.0
Units
V
V
V
TABLE
5.
INPUT
FREQUENCY
CHARACTERISTICS,
V
CC
=
V
CCA
=
V
CCO
=
3.3V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
10
40
MHz
f_IN
Input Frequency CLK, nCLK; NOTE 1
S_CLOCK
10
40
MHz
40
MHz
NOTE 1: For the differential input and TEST_CLK frequency range, the M value must be set for the VCO to operate within
the 250MHz to 700MHz range. Using the minimum input frequency of 10MHz, valid values of M are 25 ≤ M ≤ 70.
Using the maximum frequency of 40MHz, valid values of M are 7 ≤ M ≤ 17.
TABLE 6. AC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
F
Output Frequency
OUT
31.25
700
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1
fVCO > 350MHz
25
tjit(per) Period Jitter, RMS
fOUT > 100MHz
5
tsk(o) Output Skew; NOTE 1, 2
15
t_R / t_F
Output Rise/Fall Time
20% to 80%
200
700
M, N to nP_LOAD
5
t_S
Setup Time S_DATA to S_CLOCK
5
S_CLOCK to S_LOAD
5
M, N to nP_LOAD
5
t_H
Hold Time S_DATA to S_CLOCK
5
S_CLOCK to S_LOAD
5
odc
Output Duty Cycle
N>1
47
53
t_PW
Output Pulse Width
N=1
t_PERIOD/2 - 150
t_PERIOD/2 + 150
t_LOCK
PLL Lock Time
1
See Parameter Measurement Information section.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
Units
MHz
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
ps
ms
IDT^™ / ICS^™ 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER
6
ICS8432DY-101 REV. C APRIL 10, 2007