ICS8432-101_07 Datasheet, PDF (4/20 Pages) Integrated Device Technology – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
MR nP_LOAD M
Inputs
Conditions
N S_LOAD S_CLOCK S_DATA
H
X
XX
X
X
X Reset. Forces outputs LOW.
L
L
Data Data
X
L
↑
Data Data
L
L
H
XX
L
L
H
XX
↑
Data on M and N inputs passed directly to the
X
X M divider and N output divider. TEST output
forced LOW.
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
L
Data
Contents of the shift register are passed to the
M divider and N output divider.
L
H
XX
↓
L
Data M divider and N output divider values are latched.
L
H
XX
L
L
H
XX
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
X
X Parallel or serial inputs do not affect shift registers.
↑
Data S_DATA passed directly to M divider as it is clocked.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
VCO Frequency
(MHz)
M Divide
256
M8
128
M7
64
M6
32
M5
16
M4
8
M3
4
M2
2
M1
1
M0
200
8
0
0
0
0
0
1
0
0
0
225
9
0
0
0
0
0
1
0
0
1
250
10
0
0
0
0
0
1
0
1
0
275
11
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
26
0
0
0
0
1
1
0
1
0
675
27
0
0
0
0
1
1
0
1
1
700
28
0
0
0
0
1
1
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to differential input or TEST_CLK input frequency
of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
N1
N0
0
0
0
1
1
0
1
1
N Divider Value
1
2
4
8
Output Frequency (MHz)
Minimum Maximum
250
700
125
350
62.5
175
31.25
87.5
IDT^™ / ICS^™ 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER
4
ICS8432DY-101 REV. C APRIL 10, 2007