ICS8432-101_07 Datasheet, PDF (10/20 Pages) Integrated Device Technology – 700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

ICS8432-101
700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V and V must meet the
SWING
OH
V and V input requirements. Figures 4A to 4E show interface
PP
CMR
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
50
50
FIGURE 4A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
50
50
R3
50
FIGURE 4B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3
R4
125
125
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
84
84
FIGURE 4C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
LVPECL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
R3
R4
125 125
C1
C2
R5
100 - 200
R6
100 - 200
R1
R2
84
84
3.3V
CLK
nCLK _HiPerClockS
Input
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
Zo = 50 Ohm
LVDS_Driv er
R1
100
Zo = 50 Ohm
3.3V
CLK
nCLK _{Receiv er}
FIGURE 4D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
IDT^™ / ICS^™ 700MHZ, 3.3V LVPECL FREQUENCY SYNTHESIZER
10
ICS8432DY-101 REV. C APRIL 10, 2007