ICS83908I-02 Datasheet, PDF (6/16 Pages) Integrated Device Technology – LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER

ICS83908I-02
LOW SKEW, 1-TO-8 CRYSTAL-TO-LVCMOS FANOUT BUFFER
PRELIMINARY
TABLE 6C. AC CHARACTERISTICS, V_DD = 3.3V ± 5%, V_DDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
f_MAX
tp_LH
tsk(o)
Parameter
Output Frequency
w/External
XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Test Conditions
Minimum Typical Maximum Units
10
40
MHz
200
MHz
2.5
ns
TBD
ps
tsk(pp)
tjit(Ø)
t_R / t_F
odc
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
25MHz, (100Hz - 1MHz)
20% to 80%
TBD
ps
0.22
ps
487
ps
50
%
t_EN
Output Enable Time; NOTE 5
10
ns
t_DIS
Output Disable Time; NOTE 5
8
ns
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6D. AC CHARACTERISTICS, V_DD = V_DDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol
f_MAX
tp_LH
tsk(o)
Parameter
Output Frequency
w/External
XTAL
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Test Conditions
Minimum Typical Maximum Units
10
40
MHz
200
MHz
2.3
ns
TBD
ps
tsk(pp)
tjit(Ø)
t_R / t_F
odc
Part-to-Part Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
25MHz, (100Hz - 1MHz)
20% to 80%
TBD
ps
0.29
ps
470
ps
50
%
t_EN
Output Enable Time; NOTE 5
10
ns
t_DIS
Output Disable Time; NOTE 5
8
ns
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V_DDO/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
IDT^™ / ICS^™ LVCMOS FANOUT BUFFER
6
ICS83908AGI-02 REV. B JULY 24, 2007