ICS810001-21 Datasheet, PDF (6/19 Pages) Integrated Circuit Systems – FEMTOCLOCKS-TM DUAL VCXO VIDEO PLL

ICS810001-21 Data Sheet
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
Table 3D. CLK_SEL Function Table
Input
CLK_SEL Operation
0 (default) Selects CLK0 as PLL reference input.
1
Selects CLK1 as PLL reference input.
Table 3E. MR Master Reset Function Table
Input
MR
Operation
0 (default) Normal operation, internal dividers and the output Q are enabled.
1
Internal dividers are reset. Q output is in logic low state (with OE = 1).
Table 3F. FemtoCLock PLL Feedback Divider Function Table
Input
MF
Operation
0 (default) Selects MF = 22. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 22.
1
Selects MF = 24. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 24.
Table 3G. PLL Output Divider Function Table
Input
N1
N0
Operation
0 (default)
0 (default) Output divider N = 4.
0
1
Output divider N = 8.
1
0
Output divider N = 12.
1
1
Output divider N = 18.
Table 3H. PLL BYPASS Logic Function Table
Input
nBP1
nBP0
Operation
0
0
1
1 (default)
0
1
0
1 (default)
VCXO-PLL mode: The input reference frequency is divided by the pre-divider P and is multiplied by the
VCXO-PLL. f_OUT = (f_REF ÷ P) * M.
Test mode: The input reference frequency is divided by the pre-divider P and the output divider N and
bypasses both PLLs. f_OUT = f_REF ÷ (P * N).
FemtoClock Mode: The input reference frequency is divided by the pre-divider P multiplied by the 2^nd PLL
(FemtoClock, MF). The 1^st PLL (VCXO-PLL, M) is bypassed. This mode does not support jitter
attenuatiion. f_OUT = (f_REF ÷ P) * MF ÷ N.
Dual PLL Mode: both PLLs are cascaded for jitter attenuation and frequency multiplication.
f_OUT = (f_REF ÷ P) * M * MF ÷ N.
ICS810001DK-21 REVISION B APRIL 13, 2010
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©2010 Integrated Device Technology, Inc.