ICS810001-21 Datasheet, PDF (13/19 Pages) Integrated Circuit Systems – FEMTOCLOCKS-TM DUAL VCXO VIDEO PLL

ICS810001-21 Data Sheet
FEMTOCLOCK™ DUAL VCXO VIDEO PLL
Schematic Example
Figure 3 shows an example of the ICS810001-21 application
schematic. In this example, the device is operated at V_DD = V_DDX =
V_DDO = V_DDA= 3.3V. The decoupling capacitors should be located as
close as possible to the power pin. The input is driven by a 3.3V 17Ω
LVCMOS driver. An optional 3-pole filter can also be used for
additional spur reduction. It is recommended that the loop filter
components be laid out for the 3-pole option. This will also allow the
2-pole filter to be used. For the LVCMOS output, a termination
example is shown in this schematic. For more termination
approaches, please refer to the LVCMOS Termination Application
Note.
3-pole loop filter example -
(optional)
LF0
R6
LF1
Rs1
TBD
TBD
Cs1
TBD
Cp1
TBD
Cp2
TBD
2-pole loop filter
Cs
.22uF
Rs
150K
Cp
.001uF
VDD
Q1
R1
VDD
Q2
33
Driv er_LVCMOS
R2
Zo = 50
33
TL2
Driv er_LVCMOS
C1spare
X1
12pF
C2spare
VDDX
VDD
Rset 2.21K
Zo = 50
TL1
U1
1
2
3
LF1
LF0
4
5
6
7
8
ISET
VDD
nBP0
GND
CLK_SEL
CLK1
VDD
MR Control
C3 spare
X2
12pF
VDD
C4 spare
Logic Control Input Examples
Set Logic
Set Logic
VDD
VDD
Input to '1'
Input to '0'
RU1
1K
To Logic
Input
pins
RD1
Not Install
RU2
Not Install
To Logic
Input
pins
RD2
1K
N0
N1
24
23
22
nBP1
OE
GND
Q
VDDO
21
20
19
18
17
VDDA
VDD
R5
33
VDDA
Zo = 50
TL3
Receiv er
Pin4
Pin11
C5
.01uF
C6
.01uF
Pin18
Pin25
C7
.01uF
C8
.01uF
VDD
R3
10
VDDA
C9
C10
10uF
.01uF
R4
10
VDDX
C11
C12
10uF
.01uF
810001-21 Schematic
Figure 3. ICS810001-21 Schematic Example
ICS810001DK-21 REVISION B APRIL 13, 2010
13
©2010 Integrated Device Technology, Inc.