9ZXL1530_15 Datasheet, PDF (6/19 Pages) Integrated Device Technology – 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

9ZXL1530
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
Electrical Characteristics–Input/Supply/Common Output Parameters
TA = TCOM; Supply Voltage VDD/VD DA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
Ambient Operating
Tem peratu re
Input High Voltage
Input Low Voltage
SYM BOL
CONDITIONS
M IN
T_COM
VIH
VIL
IIN
Commmercial range
0
Single-ended inputs, except SMBus, low threshold
and tri-level inputs
Single-ended inputs, except SMBus, low threshold
and tri-level inputs
Single-ended inputs, VIN = GND, VIN = VDD
2
GND - 0.3
-5
TYP
MAX
70
VD D + 0.3
0.8
5
Single-ended inputs
Input Current
I_{IN P}
VIN = 0 V; Inputs with internal pull-up resistors
-20 0
2 00
VIN = VDD; Inputs with internal pull-down resistors
Input Frequency
Pin Inductance
Cap ac itan ce
F_ibyp
Fip ll
F_{ip ll}
L_pin
CIN
C_{IN DIF_IN}
C_OUT
V_DD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
V_DD = 3.3 V, 133.33MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
33
1 50
90
1 00.00
1 10
12 0
1 33.33
1 47
7
1.5
5
1.5
2.7
6
C lk Stabilization
T_STAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
1
UNITS NOTES
°C
1
V
1
V
1
uA
1
uA
1
M Hz
2
M Hz
2
M Hz
2
nH
1
pF
1
pF
1,4
pF
1
ms
1,2
Input SS Modulation
Frequen cy
f_{MOD IN}
Allowable Frequency
(Triangular Modulation)
30
33
kHz
1
Tdrive_PD#
t_{D RVPD}
DIF output enable after
PD# de-assertion
Tfall
tF
Fall time of control inputs
Trise
t_R
Rise time of control inputs
SMBus Input Low Voltage
V_{IL SMB}
SMBus Input High Voltage VIHSM B
2.1
SMBus Output Low Voltage VOL SMB
@ I_{PU LLU P}
SMBus Sink Current
IPUL LUP
@ VOL
4
Nominal Bus Voltage
V_{D DSMB}
3V to 5V +/- 10%
2.7
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
t_{F SMB}
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating Frequency fMINSM B
Minimum SMBus operating frequency
10 0
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4_{DIF_IN input}
5_{The differential input clock must be running for the SMBus to be active}
3 00
us
1,3
5
ns
1,2
5
ns
1,2
0.8
V
1
VDD SMB
V
1
0.4
V
1
mA
1
5.5
V
1
1 000
ns
1
3 00
ns
1
kHz
1,5
IDT® 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
6
9ZXL1530
REV D 112015