9ZXL1530_15 Datasheet, PDF (2/19 Pages) Integrated Device Technology – 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

9ZXL1530
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDDA 1
GNDA 2
100M_133M# 3
48 VDDIO
47 GND
46 DIF_9#
HIBW_BYPM_LOBW# 4
CKPWRGD_PD# 5
GND 6
45 DIF_9
44 DIF_8#
43 DIF_8
VDDR 7
DIF_IN 8
DIF_IN# 9
SMB_A0_tri 10
SMBDAT 11
9ZXL1530
42 GND
41 VDD
40 DIF_7#
39 DIF_7
38 DIF_6#
SMBCLK 12
37 DIF_6
SMB_A1_tri 13
36 VDDIO
FBOUT_NC# 14
35 GND
FBOU T_NC 15
GND 16
34 DIF_5#
33 DIF_5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
Power Management Table
Inputs
CK PW RGD_PD#
0
1
D IF_IN/
DIF_IN#
X
Run ning
Control Bits
SMBus
EN bit
X
0
1
Outputs
DIF_x/ FBOUT_NC/
DIF_x# FBOU T_NC#
Low /Low
Low /Low
Ru nnin g
L ow/Low
Running
Running
PLL State
OFF
ON
ON
Power Connections
Pin Number
VDD
VDD IO
GND
1
2
7
6
26, 41, 58
19,31,36,48,51 ^{16,20,25,32,3}
,63
5 ,42,4 7,52, 57
,64
De scr iption
Analog PLL
Analog Input
D IF clocks
Functionality at Power-up (PLL mode)
100M _13 3M#
1
0
DIF_IN
(M Hz)
100. 00
133. 33
DIFx
(MHz)
DI F_IN
DI F_IN
PLL Operating Mode
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW)
00
Mid (Bypass)
01
High (PLL High BW)
11
NOTE: PLL is off in Bypass mode
Tri-Level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2 <V in< 1.8V
Vin > 2.2V
IDT® 15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
2
9ZXL1530
REV D 112015