71256SA20TPG Datasheet, PDF (6/8 Pages) Integrated Device Technology – CMOS Static RAM 256K (32K x 8-Bit)

IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)^(1,2,4)
tWC
ADDRESS
tAW
CS
WE
DATAOUT
DATAIN
tAS
tWP ⁽²⁾
tWR
tWHZ ⁽⁵⁾
tOW(5)
(3)
HIGH IMPEDANCE
tDW
tDH
DATAIN VALID
tCHZ ⁽⁵⁾
(3)
, ^{2948 drw 07}
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)^(1,4)
tWC
ADDRESS
tAW
CS
tAS
tCW
tWR
WE
DATAIN
tDW
tDH
DATAIN VALID
2948 drw 08
,
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
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