71256SA20TPG Datasheet, PDF (4/8 Pages) Integrated Device Technology – CMOS Static RAM 256K (32K x 8-Bit)

IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%)
71256SA12
71256SA15
71256SA20
71256SA25
Symbol
Read Cycle
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC
Read Cycle Time
tAA
Address Access Time
tACS
Chip Select Access Time
12
____
15
____
20
____
25
____
ns
____
12
____
15
____
20
____
25 ns
____
12
____
15
____
20
____
25 ns
tCLZ⁽¹⁾
Chip Select to Output in Low-Z
4
____
4
____
4
____
4
____
ns
tCHZ⁽¹⁾
tOE
Chip Sele ct to Output in High-Z
Output Enable to Output Valid
0
6
0
7
0
10
0
11 ns
____
6
____
7
____
10
____
11 ns
tOLZ⁽¹⁾
Output Enab le to Output in Low-Z
0
____
0
____
0
____
0
____
ns
tOHZ⁽¹⁾
tOH
Output Disab le to Output in High-Z
Output Hold from Address Change
0
6
0
6
0
8
0
10 ns
3
____
3
____
3
____
3
____
ns
tPU⁽¹⁾
Chip Sele ct to Power Up Time
0
____
0
____
0
____
0
____
ns
tPD⁽¹⁾
Chip Deselect to Power Down Time
Write Cycle
____
12
____
15
____
20
____
25 ns
tWC
Write Cycle Time
tAW
Address Valid to End-of-Write
tCW
Chip Select to End-of-Write
tAS
Address Set-up Time
tWP
Write Pulse Width
tWR
Write Recovery Time
tDW
Data Valid to End-of-Write
tDH
Data Hold Time
12
____
15
____
20
____
25
____
ns
9
____
10
____
15
____
20
____
ns
9
____
10
____
15
____
20
____
ns
0
____
0
____
0
____
0
____
ns
8
____
10
____
15
____
20
____
ns
0
____
0
____
0
____
0
____
ns
6
____
7
____
11
____
13
____
ns
0
____
0
____
0
____
0
____
ns
tOW⁽¹⁾
Output Active from End-of-Write
4
____
4
____
4
____
4
____
ns
tWHZ⁽¹⁾
Write Enab le to Output in High-Z
0
6
0
6
0
10
0
11 ns
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2948 tbl 09
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