90E21 Datasheet, PDF (50/57 Pages) Integrated Device Technology – Single-Phase High-Performance Wide-Span Energy Metering IC

90E21/22/23/24
SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
6.2 SPI INTERFACE TIMING
The SPI interface timing is as shown in Figure-10, Figure-11 and
Table-12.
CS
SCLK
SDI
SDO
t_CSH
t_CSS
t_CLH
t_CLL
t_CSD
t_CLD
t_DIS t_DIH
Valid Input
t_DW
High Impedance
t_PD
Valid Output
t_DF
High Impedance
Figure-10 4-Wire SPI Timing Diagram
SCLK
SDI
SDO
t_CLH
t_CLL
t_DIS t_DIH
Valid Input
t_DW
High Impedance
t_PD
Valid Output
High Impedance
Figure-11 3-Wire SPI Timing Diagram
Table-12 SPI Timing Specification
Symbol
t_CSH^{note 1}
t_CSS^{note 1}
t_CSD^{note 1}
t_CLD^{note 1}
t_CLH
t_CLL
t_DIS
t_DIH
Description
Minimum CS High Level Time
CS Setup Time
CS Hold Time
Clock Disable Time
Clock High Level Time
Clock Low Level Time
Data Setup Time
Data Hold Time
Min.
30T ^{note 2}+10
3T+10
30T+10
1T
30T+10
16T+10
3T+10
22T+10
Typical
Electrical Specification
50
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
January 10, 2012